Phase interpolators (PIs) are used in many application including high speed input-output (I/O) receivers to generate interpolated signals from input clock signals. These interpolated signals are used to sample input data received by the I/O receiver. As power consumption requirements for a processor are becoming stringent and processors are required to operate at lower power supply levels, for example 0.8V power supply level, performance of traditional analog-based PIs degrade.
The term “performance” herein generally refers to power supply rejection ratio (PSRR), power consumption, process-temperature-voltage (PVT) variations, area, scalability to lower power supply voltages, I/O transfer rate, etc.
A typical PI is a current mode PI. The current mode PI shows poor performance at low power supply levels because the current mode PI, being analog-based design, is highly sensitive to PVT variations, exhibits a lower power supply rejection ratio (PSRR) due to high analog bias dependency on the power supply and due to low swing operation requirements, consumes higher power, and requires complementary metal-oxide semiconductor (CMOS) to current mode logic (CML) and CML to CMOS converters to operate at low voltages resulting in larger area, and has lower I/O transfer rates at lower power supply levels. Such current mode-based PIs are unable to meet the stringent low power specifications of Mobile Industry Processor Interface (MIPI®) as described in the MIPI® Alliance Specification for M-PHYSM Version 1.00.00 of Feb. 8, 2011 and approved on Apr. 28, 2011.